Semiconductor structure with capacitor landing pad and method of making the same

ABSTRACT

A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a division of U.S. application Ser. No. 17/324,114,filed on May 19, 2021, which is a division of U.S. application Ser. No.15/889,182, filed on Feb. 5, 2018. The contents of these applicationsare incorporated herein by reference.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention relates to a fabricating method of a capacitorlanding pad, and more particularly to a fabricating method which reducesthe possibility of a short circuit in the capacitor landing pad.

2. Description of the Prior Art

The dynamic random access memory (DRAM) comprises a MOS transistor, acapacitor and a contact plug. The MOS transistor is used fortransferring electric charge, the capacitor is used for storing thecharge to memorize information, and the contact plug is used as a nodecontact to electrically connect the MOS transistor and the capacitor.

As devices of the semiconductor become smaller, the process for forminga contact hole to define the position of the contact plug becomes moredifficult. Therefore, a landing pad is formed on the contact plug toensure the connection between the contact plug and the capacitor.

As the DRAM is scaled down, however, a photo mask cannot align preciselyduring the step of fabricating the landing pad. Therefore, the adjacentlanding pads connect to each other after a lithographic process, whichcauses a short circuit.

SUMMARY OF THE INVENTION

According to a preferred embodiment of the present invention, asemiconductor structure with capacitor landing pads includes asubstrate. A capacitor contact plug is disposed on the substrate. Acapacitor landing pad contacts and electrically connects the capacitorcontact plug. A bit line is disposed on the substrate. A dielectriclayer surrounds the capacitor landing pad, wherein the dielectric layerincludes a bottom surface lower than a top surface of the bit line.

According to another preferred embodiment of the present invention, afabricating method of a capacitor landing pad includes providing asubstrate, wherein a plurality of word lines are embedded in thesubstrate, a plurality of insulating layers are disposed on the wordlines, each of the insulating layers is respectively disposed directlyon one of the word lines, and an opening is defined between theinsulating layers adjacent to each other. Next, a metal layer is formedto fill in the opening, wherein the insulating layers are entirelyembedded in the metal layer. Then, a first hard mask is formed to coverthe metal layer. Subsequently, a first pattern process is performed totransform the first hard mask into a plurality of second hard masks bypatterning the first hard mask. Later, a second pattern process isperformed to transform the second hard masks into a plurality of thirdhard masks by patterning the second hard masks, wherein each of thethird hard masks does not connect to another third hard mask, and eachof the third hard masks partly overlaps one of the insulating layers.After that, the metal layer is removed by taking the third hard masks asa mask to form a trench in the metal layer, wherein the trench extendsinto the opening, a bottom of the trench is lower than a top surface ofthe insulating layers, and the trench defines the capacitor landing padon the metal layer. Finally, a dielectric layer is formed to fill up thetrench.

According to yet another preferred embodiment, a contact structureutilized for electrically connecting a capacitor and a transistor in aDRAM includes a capacitor landing pad including a first element and asecond element. The first element includes a first bottom. A secondelement includes a first top surface and a second bottom, wherein thefirst bottom contacts the first top surface, and an area of the firstbottom is smaller than an area of the first top surface. A capacitorcontact plug is disposed below the capacitor landing pad. The secondelement is disposed between the first element and the capacitor contactplug, the capacitor contact plug comprises a second top surface, thesecond top surface contacts the second bottom, and an area of the secondtop surface is smaller than an area of the second bottom.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 to FIG. 12 depict a semiconductor structure with capacitorlanding pads according to a preferred embodiment of the presentinvention, wherein:

FIG. 1 depicts a fabricating step of providing a substrate and forming ametal layer;

FIG. 2 depicts a fabricating step following FIG. 1 ;

FIG. 3 depicts a top view of a memory region shown in FIG. 2 ;

FIG. 4 depicts a fabricating step following FIG. 2 ;

FIG. 5 depicts a fabricating step following FIG. 4 ;

FIG. 6 depicts a top view of a memory region shown in FIG. 5 ;

FIG. 7 depicts a fabricating step following FIG. 5 ;

FIG. 8 depicts a top view of a memory region shown in FIG. 7 ;

FIG. 9 depicts a sectional view taken along the line AA′ shown in FIG. 8;

FIG. 10 depicts a top view of a memory region shown in FIG. 8 ;

FIG. 11 depicts a sectional view taken along the line BB′ shown in FIG.10 ; and

FIG. 12 depicts a sectional view taken along the line CC′ shown in FIG.10 .

FIG. 13 to FIG. 18 depict a contact structure utilized for electricallyconnecting a capacitor and a transistor in a DRAM, wherein:

FIG. 13 depicts a fabricating step of providing a substrate and forminga contact plug;

FIG. 14 depicts a fabricating step following FIG. 13 ;

FIG. 15 depicts a fabricating step following FIG. 14 ;

FIG. 16 depicts a fabricating step following FIG. 15 ;

FIG. 17 depicts a fabricating step following FIG. 16 ; and

FIG. 18 depicts a fabricating step following FIG. 17 .

FIG. 19 depicts a three-dimensional contact structure shown in FIG. 18and a variation of the three-dimensional contact structure shown in FIG.18 .

FIG. 20 depicts an exploded view of a three-dimensional contactstructure shown in FIG. 19 .

DETAILED DESCRIPTION

As shown in FIG. 1 , a substrate 10 is provided. The substrate 10 has amemory region 100. Numerous active areas (not shown) and numerousshallow trench isolations (STIs) 11 are disposed within the memoryregion 100. Numerous word lines 12 are embedded in the substrate 10.Several word lines 12 pass the STIs 11. Numerous bit lines (not shown)are disposed on the substrate 10, and each of the bit lines intersectswith each of the word lines 12. Moreover, an insulating layer 16 isdisposed directly on each of the word lines 12, thereby forming aplurality of insulting layers 16. Each of the insulating layers 16 mayinclude a word line mask 18 and an interlayer dielectric 20. Theinsulting layer 16 may be a single-layered material or amultiple-layered material. The insulating layers 16 may be siliconoxide, silicon nitride or silicon oxynitride. An opening 22 is definedbetween each of the insulating layers 16. A conductive layer 24 isformed conformally on the insulating layers 16 and the opening 22. Anepitaxial layer 26 is optionally formed on the substrate 10 between twoadjacent word lines 12. A doping region (not shown) can be disposedwithin the substrate 10 directly below the epitaxial layer 26. Theopening 22 is directly on the epitaxial layer 26. The substrate 10 mayfurther include a peripheral circuit region 200. A transistor 28 such asa planar transistor is disposed within the peripheral circuit region200. An opening 35 is disposed on a gate of the transistor 28. Adielectric layer 30 within the peripheral circuit region 200 covers thesubstrate 10. An opening 34 is disposed in the dielectric layer 30 onthe source/drain doping region 32. The conductive layer 24 covers aninner sidewall of the opening 34.

Then, a metal layer 36 is formed to fill in the opening 22, the opening34 and the opening 35, so that all insulating layers 16 are entirelyembedded in the metal layer 36. A top surface of the metal layer 36 ishigher than a top surface 52 of the insulating layers 16. Later, a firsthard mask 38 is formed to cover the metal layer 36.

As shown in FIG. 2 , a first pattern process is performed. In the firstpattern process, a first photoresist 40 is formed to cover the firsthard mask 38. An organic dielectric layer (ODL) 42 and asilicon-containing hard mask bottom anti-reflection coating (SHB) 44 areformed between the first photoresist 40 and the first hard mask 38 frombottom to top. Next, the first photoresist 40 is patterned. FIG. 3 is atop view of the memory region 100 shown in FIG. 2 . For the sake ofbrevity, only word lines, bit lines and the patterned first photoresistare shown in FIG. 3 . Refer to FIG. 2 together with FIG. 3 . Numerousword lines 12 intersect numerous bit lines 112. The patterned firstphotoresist 40 includes at least one first rectangular pattern 43.Numerous first rectangular patterns 43 are shown in this embodiment.Each of the first rectangular patterns 43 is parallel to each of theword lines 12. It should be noted that a photo mask shifts during anexposure process. In this embodiment, the photo mask shifts in ahorizontal direction X. The horizontal direction X is parallel to thebit lines 112. Accordingly, each of the first rectangular patterns 43covers a corresponding opening 22 and the insulating layer 16 adjacentto the corresponding opening 22. Based on the shift amount of the photomask, the first rectangular patterns 43 may cover part of the opening 22and the insulating layer 16 adjacent to the opening 22. In anotherembodiment, when the photo mask shifts, the first rectangular patterns43 may only cover part of the insulating layer 16 and cover a greaterpart of the opening 22. Because the photo mask shifts in a randomdirection, the photo mask may shift in a vertical direction Y. Thevertical direction Y is parallel to the word lines 12. In yet anotherembodiment, the photo mask may align correctly without any shift.

As shown in FIG. 4 , all the first rectangular patterns 43 aretransferred to the SHB 44 and the ODL 42. Then, the first photoresist 40is removed. Later, the pattern on the SHB 44 and on the ODL 42 istransferred to a first hard mask 38 to transform the first hard mask 38into numerous second hard masks 138. Subsequently, the SHB 44 and theODL 42 are removed. Each of the second hard masks 138 is a rectangularshape. Each of the second hard masks 138 corresponds to a position of asingle first rectangular pattern 43. Therefore, each of the second hardmasks 138 covers one opening 22 and the insulating layer 16 adjacent tothe opening 22 in the memory region 100. In this embodiment, each of thesecond hard masks 138 simultaneously covers part of the opening 22 andcovers the entire insulating layer 16 adjacent to the opening 22.

As shown in FIG. 5 , a second pattern process is performed to form asecond photoresist 240 which covers the second hard masks 138. An ODL142 and an SHB 144 can be formed from bottom to top between the secondphotoresist 240 and the second hard masks 138. FIG. 6 depicts a top viewof a memory region in FIG. 5 . For the sake of brevity, only word lines,bit lines and the patterned second photoresist are shown in FIG. 6 . Asshown in FIG. 5 , the patterned second photoresist 240 includes at leastone second rectangular pattern 46. Numerous second rectangular patterns46 are shown in this embodiment as an example. The second rectangularpatterns 46 are parallel to the bit lines 112. As before, the photo maskmay shift during an exposure process, and the photo mask shifts in arandom direction. Therefore, the photo mask may shift in a verticaldirection Y or in a horizontal direction Z. In one embodiment, the photomask does not shift. In this embodiment, the photo mask shift in thevertical direction Y. Refer to FIG. 3 together with FIG. 6 , each of thesecond rectangular patterns 46 intersects each of the first rectangularpatterns 43. The position where the second rectangular patterns 46overlaps the first rectangular patterns 43 defines a position of acapacitor landing pad on the metal layer 36.

As shown in FIG. 7 , the pattern on the second rectangular patterns 46is transferred onto the SHB 144 and the ODL 142. Next, the secondphotoresist 240 is removed. Then, the pattern on the SHB 144 and on theODL 142 is transferred to the second hard masks 138. At this point, thesecond hard masks 138 overlapping the second rectangular pattern 46remains, and the second hard masks 138 are transformed into numerousthird hard masks 238. In the memory region 100, the third hard masks 238will define the position of the capacitor landing pad. Each of the thirdhard masks 238 does not connect to another third hard mask, and each ofthe third hard masks 238 overlaps one insulating layer 16. In thisembodiment, one of the third hard masks 238 overlaps part of the opening22 and overlaps one entire insulating layer 16.

FIG. 8 is a top view following FIG. 7 . FIG. 9 is a sectional view takenalong line AA′ shown in FIG. 8 . For the sake of brevity, only wordlines, bit lines and the capacitor landing pads are shown in FIG. 8 .Refer to FIG. 8 together with FIG. 9 . At least one trench 48 is formedby removing the metal layer 36 by taking the third hard masks 238 as amask. The trench 48 extends into the opening 22. A bottom 50 of thetrench 48 is lower than a top surface 52 of the insulating layer 16.Then, the third hard masks 238 are removed.

In another embodiment, under the situation where each of the third hardmasks 238 only overlaps part of each of the insulating layers 16, thatpart of each of the insulating layers 16 will be removed during theformation of the trench 48. The space formed after removing theinsulating layers 16 becomes a part of the trench 48. This embodimenttakes the third hard masks 238 as entirely overlapping the insulatinglayers 16 as an example. After removing part of the metal layer 36, theremaining metal layer 36 on the top surface 52 of each of the insulatinglayers 16 serves as a capacitor landing pad 54. The trench 48 thereforedefines the position of the capacitor landing pad 54 on the metal layer36. There are numerous capacitor landing pads 54 in this embodiment. Thecapacitor landing pads 54 are illustrated in the diagram by reverseslashes. The metal layer 36 inside the opening 22 and below the topsurface of the insulating layer 16 serves as capacitor contact plugs 56.As mentioned above, the photo mask often shifts during alignment;therefore, the present invention makes the bottom 50 of the trench 48lower than the top surface 52 of the insulating layer 16 to ensure thecapacitor landing pads 54 do not contact each other. Furthermore, thetrench 48 forms a chessboard pattern within the memory region 100. Thetrench 48 is parallel to bit lines 112 and word lines 12. The trench 48is also perpendicular to the bit lines 112 and word lines 12. Moreover,the remaining metal layer 25 in the peripheral circuit region 200 servesas a source/drain conductive pad 58 and a gate landing pad 60.

FIG. 10 is a top view following FIG. 8 . FIG. 11 is a sectional viewtaken along the line BB′ shown in FIG. 10 . FIG. 12 is a sectional viewtaken along the line CC′ shown in FIG. 10 . For the sake of brevity,only word lines, bit lines, capacitor lading pads, and a dielectriclayer are shown in FIG. 10 . Refer to FIG. 10 together with FIG. 11 . Adielectric layer 62 is formed on the substrate 10. The dielectric layer62 within the memory region 100 forms a chessboard, and the dielectriclayer 62 fills in the trench 48 between the capacitor landing pads 54.After that, a capacitor (not shown) can be formed on the capacitorlanding pads 54. At this point, the transistors formed by the word lines12 can form a dynamic random access memory (DRAM) with a capacitor. Itshould be noted that a bottom 64 of the dielectric layer 62 is lowerthan the top surface 52 of the insulating layer 16. Moreover, as shownin FIG. 12 , the bottom 64 of the dielectric layer 62 is lower than atop surface 66 of the bit lines 112. In this way, parasitic capacitancecan be reduced.

Refer to FIG. 10 together with FIG. 12 . According to a preferredembodiment of the present invention, a semiconductor structure withcapacitor landing pads includes a substrate 10. At least a capacitorcontact plug 56 is disposed on the substrate 10. Numerous capacitorcontact plugs 56 are shown in FIG. 12 as an example. A capacitor landingpad 54 contacts and connects to one capacitor contact plug 56. There arenumerous capacitor landing pads 54. One of the capacitor landing pads 54and one of the capacitor contact plugs 56 form a step profile. A bitline 112 is disposed on the substrate 10. A dielectric layer 62surrounds the capacitor landing pads 54. The dielectric layer 62 has abottom 64 lower than a top surface 66 of the bit line 112. Moreover, afirst distance D1 is disposed between a top surface 68 of the capacitorlanding pads 54, and a top surface 70 of the substrate 10. A seconddistance D2 is disposed between the top surface 66 of the bit line 112and the top surface 70 of the substrate 70. The first distance D1 islarger than the second distance D2. A bit line mask 72 covers the bitline 112. The top surface 66 of the bit line 112 contacts the bit linemask 72. The bit line mask 72 is disposed between the capacitor landingpads 54 and the bit line 112. Moreover, the capacitor landing pads 54are on the bit line mask 72. The capacitor contact plugs 56 are belowthe bit line mask 72.

The dielectric layer surrounding the capacitor landing pads has a bottomlower than a top surface of the bit line to reduce parasiticcapacitance, and ensure the capacitor landing pads are insulated fromeach other.

FIG. 13 to FIG. 18 depict a contact structure utilized for electricallyconnecting a capacitor and a transistor in a DRAM. As shown in FIG. 13 ,a substrate 300 is provided. The substrate 300 has a memory region 400.Numerous active areas (not shown) and numerous STIs 311 are disposedwithin the memory region 400. Numerous word lines 12 are embedded in thesubstrate 300. Several word lines 312 pass the STIs 311. Numerous bitlines (not shown) are disposed on the substrate 300, and each of the bitlines intersects each of the word lines 312. Moreover, a source/draindoping region 313 is disposed between adjacent word lines 312. Thesource/drain doping region 313 and the word line 312 adjacent to thesource/drain doping region 313 form a transistor 314. Next, a firstinterlayer dielectric 316 is formed on the substrate 300. Then, numerouscontact holes 318 are formed in the first interlayer dielectric 316. Thesource/drain doping region 313 is exposed through each of the contactholes 318. Subsequently, a conductive material is formed to fill in eachof the contact holes 38. The conductive material filling in the contacthole 318 serves as a capacitor contact plug 320. The capacitor contactplug 320 electrically connects to the transistor 314 through thesource/drain doping region 313. A top surface 322 of the capacitorcontact plug 320 is aligned with a top surface 324 of the firstdielectric layer 316. The conductive material may be a single-layeredmaterial or a multiple-layered material. The conductive materialincludes doped polysilicon, CoSi, W, Cu or Al. In this embodiment, theconductive material includes polysilicon, CoSi, and W stacked frombottom to top.

As shown in FIG. 14 , a second dielectric layer 326 is formed to coverthe first dielectric layer 316. Then, a photoresist is formed on thesecond dielectric layer 326. Next, a photomask 328 is provided. Numerouspre-determined patterns 330 are formed on the photo mask 328. Thepre-determined patterns 330 are used to define a position of initialcapacitor landing pads. By using a lithographic process, thepre-determined patterns 330 will be transferred to the photoresist tomake the photoresist become a patterned photoresist 332. At this point,the patterned photoresist 332 defines the position of the initialcapacitor landing pads on the second dielectric layer 326. In this step,the position of the photo mask 328 is adjusted to make a sidewall 334 ofeach pre-determined pattern 330 align with a sidewall 336 of thecapacitor contact plug 320. Based on this embodiment, the patternedphotoresist 332 includes numerous openings 338. The second dielectriclayer 326 exposed from the openings 338 will be replaced by the initialcapacitor landing pads. The initial capacitor landing pads willhereafter be referred to as capacitor landing pads.

Refer to FIG. 14 together with FIG. 15 . The second dielectric layer 326is etched to form numerous holes 340 in the second dielectric layer 326by taking the patterned photoresist 332 as an etching mask. Later, thepatterned photoresist 332 is removed. Then, a conductive material isformed to fill in each of the holes 340. The conductive material fillingin each of the holes 340 serves as initial capacitor landing pads 342.The conductive material is preferably W, but not limited to W. Othersuitable conductive materials may be used as initial capacitor landingpads 342. Moreover, a top surface 344 of the initial capacitor landingpads 342 is aligned with a top surface 346 of the second dielectriclayer 326. A sidewall 348 of each initial capacitor landing pad 342 isaligned with the sidewall 336 of the capacitor contact plug 320. Each ofthe initial capacitor landing pads 342 includes a height H. This heightH equals a length of the sidewall 348.

According to another preferred embodiment of the present invention, thecapacitor contact plug 320 and the initial capacitor landing pads 342may be formed simultaneously. For example, numerous contact holes 318are formed in the first dielectric layer 316 as shown in FIG. 13 .Instead of first filling the conductive material, the steps of formingthe patterned photoresist 332 and numerous holes 340 in FIG. 14 and FIG.15 are performed before forming the conductive material. Next, theconductive material is filled into the contact holes 336 and holes 340to form the capacitor contact plug 320 and the initial capacitor landingpads 342 simultaneously. As shown in FIG. 16 , after forming thecapacitor contact plug 320 and the initial capacitor landing pads 342,another photoresist is formed to cover the second dielectric layer 326.Then, the photoresist is patterned by using the photo mask 328 via alithographic process to form a patterned photoresist 350. It should benoted that the photo mask 328 used in this embodiment is the same as thephoto mask 328 in FIG. 14 . The pre-determined pattern 330 in thisembodiment defines the trimming position of the initial capacitorlanding pads 342; therefore, the pre-determine pattern 330 overlaps partof the initial capacitor landing pads 342, and the sidewall 334 of theinitial capacitor landing pads 342 does not align with the sidewall 336of the capacitor contact plug 320. The pre-determined pattern 330 inFIG. 14 , however, is to define the position of the initial capacitorlanding pads 342. Moreover, in this embodiment, the patternedphotoresist 350 includes numerous openings 350. Each of the openings 352corresponds to one initial capacitor landing pad 342. Part of theinitial capacitor landing pad 342 is exposed through the opening 352 towhich the initial capacitor landing pad 342 corresponds. In detail, across-section of the initial capacitor landing pad 342 has a width W. Atleast one third to two thirds of the width W is exposed through oneopening 352. Furthermore, part of the second dielectric layer 326 isexposed through the openings 352. This embodiment takes one half of thewidth W exposed through one opening 352 as an example.

Refer to FIG. 16 together with FIG. 17 . The exposed initial capacitorlanding pads 342 and the dielectric layer 326 are removed by taking thepatterned photoresist 350 as a mask to form numerous holes 354. At thispoint, at least one third to two thirds (calculated from the top surface344) of the height H of each of the initial capacitor landing pads 342is removed. In this embodiment, one half of the height H is removed. Atthis point, the initial capacitor landing pads 342 become the capacitorlanding pads 356. Each of the capacitor landing pads 356 and thecapacitor contact plug 320 forms a contact structure 358 of the presentinvention.

As shown in FIG. 18 , the patterned photoresist 350 is removed. Then, adielectric layer 360 is formed to fill in the holes 350. A top surface362 of the dielectric layer 360 is aligned with a top surface 346 of thedielectric layer 326. Later, a capacitor 366 is formed to connect andcontact one of the capacitor landing pads 356.

An example (a) in FIG. 19 depicts a three-dimensional contact structureshown in FIG. 18 . An example (b) in FIG. 19 depicts a variation of thethree-dimensional contact structure shown in FIG. 18 . FIG. 20 depictsan exploded view of a three-dimensional contact structure shown in theexample (a) of FIG. 19 . Although only the example (a) is shown inexploded view, an exploded view of the example (b) is almost the same asthat of the example (a), except that the area of the first element isdifferent.

As shown in the example (a) in FIG. 19 and FIG. 20 , a contact structure358 includes a capacitor landing pad 356 and a capacitor contact plug320. The capacitor landing pad 356 includes a first element 368 and asecond element 370. The second element 370 is disposed between the firstelement 368 and the capacitor contact plug 320. The first element 368includes a first bottom 372. The second element includes a first topsurface 374 and a second bottom 376. The first bottom 372 contacts thefirst top surface 374. The area of the first bottom 372 is smaller thanthe area of the top surface 374. The capacitor contact plug 320 includesa second top surface 378. The second top surface 378 contacts the secondbottom 376. The area of the second top surface 378 is smaller than thearea of the second bottom 376. The first element 368 intersects thecapacitor contact plug 320. The first bottom 372 does not overlap thesecond top surface 378. The first top surface 374 is opposite to thesecond bottom 376. The first top surface 374 has the same shape and thesame size as that of the second bottom 376.

The difference between the example (b) and the example (a) is that thesecond top surface 378 in the example (b) only overlaps part of thefirst bottom 372. The first bottom 372 in the example (a) does notoverlap the second top surface 378. These differences are due todifferent positions of the photo mask 328.

Part of the capacitor landing pad of the present invention is removed tomake the first bottom of the first element smaller than the first topsurface of the second element. Therefore, the distance between thecapacitor and the first element becomes longer, reducing the possibilityof a short circuit.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

What is claimed is:
 1. A contact structure utilized to electricallyconnect a capacitor and a transistor in a DRAM, the contact structurecomprising: a capacitor landing pad comprising: a first elementcomprising a first bottom; a second element comprising a first topsurface and a second bottom, wherein the first bottom contacts the firsttop surface, and an area of the first bottom is smaller than an area ofthe first top surface; and a capacitor contact plug, wherein the secondelement is disposed between the first element and the capacitor contactplug, the capacitor contact plug comprises a second top surface, thesecond top surface contacts the second bottom, and an area of the secondtop surface is smaller than an area of the second bottom.
 2. The contactstructure utilized to electrically connect the capacitor and thetransistor in the DRAM of claim 1, wherein the first element intersectsthe capacitor contact plug.
 3. The contact structure utilized toelectrically connect the capacitor and the transistor in the DRAM ofclaim 2, wherein the entire first bottom does not overlap the second topsurface.
 4. The contact structure utilized to electrically connect thecapacitor and the transistor in the DRAM of claim 1, wherein an area ofthe first bottom is larger than an area of the second top surface. 5.The contact structure utilized to electrically connect the capacitor andthe transistor in the DRAM of claim 4, wherein the second top surfaceonly partly overlaps the first bottom.
 6. The contact structure utilizedto electrically connect the capacitor and the transistor in the DRAM ofclaim 1, further comprising a capacitor contacting the capacitor landingpad.
 7. The contact structure utilized to electrically connect thecapacitor and the transistor in the DRAM of claim 1, wherein the firsttop surface is opposite to the second bottom, and the first top surfaceand the second bottom have the same shape.
 8. The contact structureutilized to electrically connect the capacitor and the transistor in theDRAM of claim 1, further comprising: a transistor electricallyconnecting to the capacitor contact plug; and a capacitor electricallyconnecting to the capacitor landing pad.